IET Computers and Digital Techniques

IET Computers and Digital Techniques Q3区

  • 期刊收录:
  • SCIE
  • Scopus
  • DOAJ开放期刊
IET计算机和数字技术杂志
  • ISSN:

    1751-8601

  • 影响因子:

    1.1

  • 是否综述期刊:

  • 是否预警:

    不在预警名单内

  • 是否OA:

  • jcr分区:

    Q3区

  • 发刊时间:

    2007

  • 发刊频率:

    Bi-monthly

  • 中科院大类:

    计算机科学

出版信息
  • 出版国家

    ENGLAND

  • 出版社:

    Wiley

  • 数据库:

    SCIE,Scopus,DOAJ开放期刊

  • 年发文量:

    11

  • 国人发稿量:

    0.77

  • 自引率:

    -

  • 平均录取率:0
  • 平均审稿周期:12周,或约稿
  • 版面费:US$2200
  • 研究类文章占比100.00%
  • 被引用占比:-
  • 偏重研究方向:工程技术-计算机:理论方法
杂志官网 投稿链接 关注公众号

期刊关键词

SCIEScopusDOAJ开放期刊COMPUTER SCIENCETHEORY & METHODSQ3计算机科学4区计算机:理论方法

期刊简介

IET Computers & Digital Techniques publishes technical papers describing recent research and development work in all aspects of digital system-on-chip design and test of electronic and embedded systems, including the development of design automation tools (methodologies, algorithms and architectures). Papers based on the problems associated with the scaling down of CMOS technology are particularly welcome. It is aimed at researchers, engineers and educators in the fields of computer and digital systems design and test.The key subject areas of interest are:Design Methods and Tools: CAD/EDA tools, hardware description languages, high-level and architectural synthesis, hardware/software co-design, platform-based design, 3D stacking and circuit design, system on-chip architectures and IP cores, embedded systems, logic synthesis, low-power design and power optimisation.Simulation, Test and Validation: electrical and timing simulation, simulation based verification, hardware/software co-simulation and validation, mixed-domain technology modelling and simulation, post-silicon validation, power analysis and estimation, interconnect modelling and signal integrity analysis, hardware trust and security, design-for-testability, embedded core testing, system-on-chip testing, on-line testing, automatic test generation and delay testing, low-power testing, reliability, fault modelling and fault tolerance.Processor and System Architectures: many-core systems, general-purpose and application specific processors, computational arithmetic for DSP applications, arithmetic and logic units, cache memories, memory management, co-processors and accelerators, systems and networks on chip, embedded cores, platforms, multiprocessors, distributed systems, communication protocols and low-power issues.Configurable Computing: embedded cores, FPGAs, rapid prototyping, adaptive computing, evolvable and statically and dynamically reconfigurable and reprogrammable systems, reconfigurable hardware.Design for variability, power and aging: design methods for variability, power and aging aware design, memories, FPGAs, IP components, 3D stacking, energy harvesting.Case Studies: emerging applications, applications in industrial designs, and design frameworks.

IET Computers & Digital Techniques出版技术论文,介绍电子和嵌入式系统的数字片上系统设计和测试的各个方面的最新研究和开发工作,包括设计自动化工具(方法、算法和架构)的开发。基于CMOS技术缩小相关问题的论文尤其受欢迎。主要面向计算机和数字系统设计与测试领域的研究人员、工程师和教育工作者。主要兴趣领域包括:设计方法和工具:CAD/EDA工具、硬件描述语言、高级和架构综合、硬件/软件协同设计、基于平台的设计、3D堆叠和电路设计、片上系统架构和IP内核、嵌入式系统、逻辑综合、低功耗设计和功耗优化。仿真、测试和验证:电气和时序仿真、基于仿真的验证、硬件/软件协同仿真和验证、混合域技术建模和仿真、后硅验证、功率分析和估计、互连建模和信号完整性分析、硬件信任和安全性、可测试性设计、嵌入式核心测试、片上系统测试、在线测试、自动测试生成和延迟测试、低功率测试可靠性、故障建模和容错。2处理器和系统结构:众核系统、通用和专用处理器、DSP应用的计算算术、算术和逻辑单元、高速缓存、内存管理、协处理器和加速器、片上系统和网络、嵌入式内核、平台、多处理器、分布式系统、通信协议和低功耗问题。嵌入式内核、FPGA、快速原型设计、自适应计算、可演化、静态和动态可重新配置和可重新编程系统、可重新配置硬件。针对可变性、功耗和老化的设计:可变性设计方法、功耗和老化感知设计、存储器、FPGA、IP组件、3D堆叠、能量收集。案例研究:新兴应用、工业设计应用和设计框架。

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分区信息

中科院分区(2023年12月最新升级版)
  • 大类学科
  • 分区
  • 小类学科
  • 分区
  • Top期刊
  • 综述期刊
  • 计算机科学
  • 4区
  • COMPUTER SCIENCE
    THEORY & METHODS
    计算机:理论方法
  • 4区
JCR分区、WOS分区等级:Q3
  • 版本
  • 按学科
  • 分区
  • WOS期刊SCI分(2022-2023年最新版)
  • COMPUTER SCIENCE,THEORY & METHODS
  • Q3
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